MUET logo

Transient and Stability Analysis of Voltage Switch Charge Pump PLL

Authors

  • Shazia Feroz

    Department of Electronics Engineering Technology, Benazir Bhutto Shaheed University of Technology and Skills Development, Khairpur Mirs, Pakistan
    Author

  • Ehsan Ali

    Department of Electronics Engineering, Quaid-e-Awam University of Engineering and Technology, Nawabshah, Pakistan
    Author

  • Darshna Narwani

    Mehran University of Engineering and Technology, Shaheed Zulfiqar Ali Bhutto Campus, Khairpur Mirs, Pakistan
    Author

DOI:

https://doi.org/10.22581/0805

Keywords:

Phase-locked Loop, Charge Pump PLL, Transient Response, Stability Analysis, Loop Filter Design, Phase Margin

Abstract

Phase-Locked Loops (PLLs) are widely used in modern communication, sensing, and digital systems for frequency synthesis, clock generation, and synchronization. Understanding their transient behavior and stability is essential for achieving fast, accurate, and reliable operation. This paper presents an analytical study of the transient dynamics and stability of second- and third-order Voltage Switch Charge Pump Phase-Locked Loop (VSCP-PLL) architectures for high-speed communication and sensing. A unified framework combines small-signal linearization, nonlinear modeling, and state-space formulation for both loop orders. For the second-order loop, closed-form natural frequency and damping ratio expressions enable direct prediction of overshoot, settling time, and lock behavior. The third-order model captures added pole–zero interactions and higher-order coupling, explaining phase accumulation and stability degradation. Key parameters—charge-pump current, loop-filter pole–zero placement, VCO gain, and divider ratio—are examined in relation to transient response and phase/frequency error. Stability margins are quantified through Bode analysis, highlighting the reductions in phase and gain margins caused by the extra pole. Controllability and observability are verified to support digital-assist and adaptive control. Simulations and event-driven transients validate the derived stability analysis and robust design region. Results show that third-order filtering improves spur and ripple suppression but increases mismatch sensitivity and lock-time variability. MATLAB R2020a and Simulink are used for the simulations.

Downloads

References

[1] P. Zhou, C. Li, Z. Kang, S. Zheng, L. Wu, and Q. Xue, “A 5.91–8.94 GHz phase-locked loop in 65 nm CMOS for 5G applications,” Microwave and Optical Technology Letters, vol. 65, no. 4, pp. 975–980, 2023.

[2] B. Razavi, “The Role of PLLs in Future Wireline Transmitters,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 8, pp. 1786–1793, 2009.

[3] M. Bhardwaj and S. Pandey, “Mathematical modelling and simulation of a wideband PLL for application in frequency synthesizers,” e-Prime Advances in Electrical Engineering, Electronics and Energy, vol. 5, p. 100216, 2023.

[4] T. V. H. Nguyen and C.-K. Pham, “A dual-mode adaptive bandwidth PLL for improved lock performance,” Electronics, vol. 14, no. 20, p. 4008, 2025.

[5] S. Kumar, “Stability Limited PLL bandwidth Derivation using Impulse Invariance Method,” in 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 1–4, IEEE, 2023.

[6] M. A. Ansari, S. H. Saeed, D. Balodi, I. U. Khan, and Z. H. Khan, “Design and Performance Analysis of a Low Jitter Charge Pump-Phase Locked Loop Architecture and Loop Filter in CMOS Process,” Journal of Electrical Systems, 2024.

[7] K. Sogo, A. Toya, and T. Kikkawa, “A ring-VCObased sub-sampling PLL CMOS circuit with −119 dBc/Hz phase noise and 0.73 ps jitter,” in 2012 Proceedings of the ESSCIRC (ESSCIRC), pp. 253– 256, IEEE, 2012.

[8] A. Brambilla, D. Linaro, and M. Storace, “Nonlinear behavioural model of charge pump PLLs,” International Journal of Circuit Theory and Applications, vol. 41, no. 10, pp. 1027–1046, 2013.

[9] E. Ali, C. Hangmann, C. Wiegand, C. Hedayat, and D. Kraus, “Event Driven simulation of the second order voltage operated CP-PLL,” in SAME conf., (Nice, France), 2012.

[10] S. M. Dartizio, F. Tesolin, M. Mercandelli, A. Santiccioli, A. Shehata, S. Karman, L. Bertulessi, F. Buccoleri, L. Avallone, A. Parisi, A. L. Lacaita, M. P. Kennedy, C. Samori, and S. Levantino, “A 12.9-to-15.1-ghz digital pll based on a bang-bang phase detector with adaptively optimized noise shaping,” IEEE Journal of Solid-State Circuits, vol. 57, no. 6, pp. 1723–1735, 2022.

[11] Y. Wang, Y. Liu, H. Xu, Z. Li, and Z. Li, “A Wideband and Low Reference Spur PLL with Clock Feedthrough Suppressed and Low Current Mismatch Charge Pump and Symmetrical CML Divider,” Electronics, vol. 12, no. 19, p. 4164, 2023.

[12] E. Ali, A. S. Sand, F. Memon, G. M. Bhuto, and N. Nizamani, “Stability Consideration of the Voltage Switched Charge-pump Phase Locked Loop using Linear Approach,” Research Journal of Applied Sciences, Engineering and Technology, vol. 13, no. 3, pp. 257–264, 2016.

[13] P. Paliwal, D. Pal, and S. Gupta, “Stability Analysis for Fast Settling Switched DPLL,” arXiv preprint arXiv:1806.01209, 2018.

[14] C. D. Hedayat, A. Hachem, Y. Leduc, and G. R. Benbassat, “Modeling and Characterization of the 3rd Order Charge-Pump PLL: a Fully Event-driven Approach,” Analog Integrated Circuits and Signal Processing, vol. 19, no. 1, pp. 25–45, 1999.

[15] E. Ali, F. Haddad, W. Rahajandraibe, N. Nizamani, C. Hangmann, and C. Hedayat, “Autonomous Event Driven Model of Second Order Voltage Switched Charge Pump PLL,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 12, pp. 2903–2907, 2020.

[16] X. Wei, R. Yin, L. Hou, W. Xu, and B. Wei, “Design and Analysis of the Self-Biased PLL with Adaptive Calibration for Minimum of the Charge Pump Current Mismatch,” Electronics, vol. 11, no. 14, p. 2133, 2022.

[17] E. Ali, D. Narwani, A. M. Bughio, N. Nizamani, S. H. Siyal, and A. R. Khatri, “Analyzing the impact of loop parameter variations on the transient response of second order voltage-switched CPPLL,” Engineering, Technology & Applied Science Research, vol. 11, no. 1, pp. 6687–6690, 2021.

[18] N. Kuznetsov, A. Matveev, M. Yuldashev, and R. Yuldashev, “Nonlinear analysis of charge-pump phase-locked loop: The hold-in and pull-in ranges,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 10, pp. 4049–4061, 2021.

[19] N. V. Kuznetsov, M. Y. Lobachev, E. V. Kudryashova, O. A. Kuznetsova, and D. G. Arseniev, “The Viterbi problem on coincidence of phase-locked loop lock-in, pull-in, and hold-in ranges,” Nonlinear Dynamics, vol. 113, no. 11, pp. 13771–13789, 2025.

[20] M. K. Saraswat, R. Mahadev, S. B. Yerragudi, K. M. Le, and Z. Abbas, “A process and temperature compensation technique for ring-VCO in charge-pump pll,” in 2024 IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 586–590, IEEE, 2024.

[21] E. Ali, W. Rahajandraibe, F. Haddad, C. Hedayat, and C. Hangmann, “Simulative characterization of the stability for second order voltage switched CPPLL,” in 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 153–156, IEEE, 2013.

[22] D. Gaidioz, A. Cathelin, and Y. Deval, “28-nm FD-SOI CMOS submilliwatt ring oscillator-based dual-loop integer-N PLL for 2.4-GHz Internetof-Things applications,” IEEE Transactions on Microwave Theory and Techniques, vol. 70, no. 4, pp. 2207–2216, 2022.

[23] Y. Zhao, M. Forghani, and B. Razavi, “A 20-GHz PLL with 20.9-fs random jitter,” IEEE Journal of Solid-State Circuits, vol. 58, no. 6, pp. 1597–1609, 2022.

[24] W. Tao, W. Zhao, R. B. Staszewski, F. Lin, and Y. Hu, “An 18.8-to-23.3 GHz ADPLL based on charge-steering-sampling technique achieving 75.9 fs RMS jitter and −252 dB FoM,” in 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), pp. 1–2, IEEE, 2023.

[25] M. AlSuwaidia, N. Quadir, L. Albasha, and H. Mir, “A low power frequency synthesizer design for RF wireless power transfer applications,” in 2024 6th International Youth Conference on Radio Electronics, Electrical and Power Engineering (REEPE), pp. 1–5, IEEE, 2024.

[26] P. P. Chary, R. Shaik Peerla, and A. Dutta, “A Simplified Gm-C Filter Technique for Reference Spur Reduction in Phase-Locked Loop,” Journal of Low Power Electronics and Applications, vol. 14, no. 1, p. 17, 2024.

[27] E. Ali, C. Hangmann, C. Hedayat, F. Haddad, W. Rahajandraibe, and U. Hilleringmann, “Event Driven Modeling and Characterization of the Second Order Voltage Switched Charge Pump PLL,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 3, pp. 347–358, 2016.

[28] L. Gupta, T. Sharma, and B. Saranga, “Ring Oscillators based All Digital Phase Locked Loop: A Comparative Study,” in 2023 International Conference on Device Intelligence, Computing and Communication Technologies (DICCT), pp. 238– 242, IEEE, 2023.

[29] V. Mazzaro and M. P. Kennedy, “A family of ΔΣ modulators with high spur immunity and low folded nonlinearity noise when used in fractionalfrequency synthesizers,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 11, pp. 4499–4509, 2022.

[30] B. Daniels, Analysis and design of high order digital phase locked loops. PhD thesis, National University of Ireland Maynooth, 2008.

Published

2026-10-01

Issue

Vol. 45 No. 4 (2026): October Issue

Section

Articles

License

Copyright (c) 2026 Mehran University Research Journal of Engineering and Technology

Creative Commons License

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

How to Cite

Transient and Stability Analysis of Voltage Switch Charge Pump PLL. (2026). Mehran University Research Journal of Engineering and Technology, 45(4), 148-155. https://doi.org/10.22581/0805

Similar Articles

31-40 of 78

You may also start an advanced similarity search for this article.