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Design and Performance Analysis of Reduced Device Count Cascaded Half Bridge Multilevel Inverter

Authors

  • Abdul Jabbar Memon

    Department of Electrical Engineering, MUET Jamshoro
    Author
  • Mukhtiar Ahmed Mahar

    Department of Electrical Engineering, MUET Jamshoro
    Author
  • Abdul Sattar Larik

    Department of Electrical Engineering, MUET Jamshoro
    Author
  • Muhammad Mujtaba Shaikh

    Department of Basic Sciences and Related Studies, MUET Jamshoro
    Author

DOI:

https://doi.org/10.22581/0652

Keywords:

Multilevel Inverter (MLI), MATLAB/Simulink, Pulse Width Modulation (PWM), Total Harmonic Distortion (THD), Photovoltaic (PV)

Abstract

The demand for renewable energy, especially PV systems, is increasing day by day. However, the efficiency of the system still remains the main concern due to the increased power switches. This research is based on the design and analysis of a reduced switch cascaded half-bridge multilevel inverter (MLI) integrated with a PV system. The proposed inverter uses only eight power switches, where two switches serve as a polarity changer and four DC sources. A Perturb and Observe (P&O) maximum power point tracking (MPPT) algorithm is implemented to control the DC-DC boost converter to track the maximum power from the PV array under variable irradiances. The whole PV boost converter MLI system is simulated in MATLAB Simulink. Simulation results show that the proposed design successfully generates the 13-level output with THD of 10.82%. This optimized design reduces the total number of components as compared to the conventional MLIs, leading to the lower switching losses, reduced cost and simpler gate driver circuitry, and improved overall system efficiency. The proposed design confirms a practical and efficient approach for enhancing the performance of PV-based renewable energy systems.

 

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Author Biography

  • Mukhtiar Ahmed Mahar, Department of Electrical Engineering, MUET Jamshoro

    Department of Electrical Engineering, MUET Jamshoro

References

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Published

2026-04-01

How to Cite

Design and Performance Analysis of Reduced Device Count Cascaded Half Bridge Multilevel Inverter. (2026). Mehran University Research Journal of Engineering and Technology, 45(2), 162-173. https://doi.org/10.22581/0652

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